Processor maker Intel recently held its annual VLSI International Symposium in Honolulu, USA, to announce the details of the Intel4 process. Intel said that compared to Intel7, Intel4 same power consumption to improve more than 20% performance, high-performance component library (library cell) density is two times, while achieving two key objectives: to meet the needs of products in development, including the PC client Meteor Lake, and to promote advanced technologies and process modules to lead Intel back to process leadership in 2025.
Intel pointed out that Intel4 in the fin pitch, contact pitch and low-level metal pitch and other critical dimensions (Critical Dimension) continue to move toward micro-shrinking, and the introduction of design technologies together with optimization, reducing the size of a single component. Through FinFET materials and structural improvements to enhance performance, Intel4 single N-type semiconductor or P-type semiconductor, the number of fins from Intel7 high-performance components library 4 to 3. The combination of these technologies enables Intel4 to significantly increase logic component density and reduce path latency and power consumption.
Intel7 introduces Self-Aligned Quad Patterning (SAQP) and Contact Over Active Gate (COAG) technologies to increase logic density. Self-Aligned Quad Patterning can reduce wafer micrograph patterns by a factor of 4 through a single micrograph and two deposition and etch steps without the problem of multiple micrograph layers aligning. Intel4 further incorporates a gridded layout scheme to simplify and regularize circuit wiring, increasing performance and improving production yields.
As the process shrinks, the metal wires and joints above the transistors also shrink. Intel4 uses a new metal formula called EnhanceCu, which uses copper as the main body of the wires and contacts, replacing Intel7's cobalt, and covers them with cobalt and tantalum; this formula combines copper's low resistance characteristics and reduces free electrons from hitting atoms and displacing them when they move, thus allowing This formula combines the low resistance characteristics of copper and reduces the electromigration phenomenon of free electrons hitting the atoms when they move, thus making the circuit fail.
Finally, the most important change in photomask pattern imaging to the wafer may be in the widespread use of EUV to simplify the process. Intel not only existing good solutions for the most critical layer using EUV, and Intel4 higher interconnect layer also use EUV, significantly reducing the number of photomasks and process steps. Reduce process complexity, but also synchronize the future process nodes to establish technology leadership and equipment capacity, Intel will use EUV more widely in these processes, the introduction of the world's first mass production of high numerical aperture (High-NA) EUV system.
